1. Field of the Invention
The present invention relates to a memory system and a method for operating the memory system. More particularly, the present invention is related to a memory system including multi-level cell (MLC) memory having a plurality of programmable levels.
2. Description of the Related Art
A prominent example for MLC memory cells having a plurality of programmable levels is Resistive Random Access Memory, particular Phase Change Memory, or Flash. PCM is a non-volatile solid-state memory technology that exploits a reversible, thermally-assisted switching of specific chalcogenides between certain states of different electrical conductivity.
PCM is a promising and advanced emerging non-volatile memory technology mainly due to its excellent features including low latency, high endurance, long retention and high scalability. PCM can be considered a prime candidate for Flash replacement, embedded/hybrid memory and storage-class memory. Key requirements for competitiveness of PCM technology can be multi-level cell functionality, in particular for low cost per bit, and high-speed read/write operations, in particular for high bandwidth. Multilevel functionality, i.e. multiple bits per PCM cell, can be a way to increase storage capacity and thereby to reduce cost.
Multi-level PCM is based on storing multiple resistance levels between a lowest (SET) and a highest (RESET) resistance value. Multiple resistance levels or levels correspond to partial-amorphous and partial-crystalline phase distributions of the PCM cell. Phase transformation, i.e. memory programming, can be enabled by Joule heating. In this regard, Joule heating can be controlled by a programming current or voltage pulse. Storing multiple resistance levels in a PCM cell is a challenging task.
In MLC PCM, the physical quantity measured during cell readout, i.e., the electrical resistance drifts upwards with time following a deterministic empirical power-law with stochastic fluctuations. In MLC Flash, the physical quantity measured is the transistor's threshold voltage, which in turn drifts upwards as a function of the number of program/erase cycles. Moreover, in solid-state memory technologies, the read signal is hampered by noise having RTN signature and 1/f characteristics. In order to increase the reliability of such devices, it can be necessary to use advanced signal processing and/or coding methods that allow the estimation and detection of the stored information levels. These types of signal processing functions use as input the soft-information from the readout signal and typically operate on a data-block basis, i.e., on a group of read-out values. The requirement for using advanced signal processing in the read process can introduce latency and data overhead which have to be kept at minimum levels for solid-state memory applications. In this context, careful design of the memory system architecture can be a key factor to achieve maximum performance with minimum circuit complexity.
A typical memory system includes of multiple memory chips which communicate with the main memory controller via a standard memory interface (MIF), e.g., LPDDR, ONFI etc. The memory controller is responsible for the memory data management and also provides the interface with the host processor (HIF). In the memory system, MLC memory chips and a CODEC can be used, wherein the CODEC is the unit that implements signal processing and coding functions based on soft-information from the read signal that is provided by the on-chip read circuitry. The goal of the CODEC unit is to provide an estimation of the stored multi-level symbols. These symbols are then translated to binary data symbols based on the applied encoding process. Typically, the estimation and detection algorithms operate in a block basis, which means that a number of cells need to be read in order for the algorithms to provide the output results.
FIGS. 1-3 show different approaches for architecture of a memory system including N memory chips 111-114, here MLC PCM, and a memory controller 180. In FIG. 1, CODEC units 140 are integrated in memory controller 180. Depending on the data management, i.e., the allocation of data to different memory chips 111-114, the total number of CODEC units 140 can be less than N allowing for more efficient CODEC utilization. However, the approach of FIG. 1 is very tied to the specific CODEC functions, which in turn depends on the memory technology and the memory system application. In addition, since CODEC units 140 operate on soft-information from the read signal, the pin and data rate requirements between memory chips 111-114 and memory controller 180 can be affected significantly.
In FIGS. 2 and 3, CODEC units 140 are decoupled from main controller 180. In FIG. 2, the respective CODEC unit 140 is integrated in memory chip 111-114. In this approach, the overall cost and the size of memory chip 111-114 increases. In FIG. 3, the respective CODEC unit 140 is implemented as a stand-alone device and a dedicated data-link (DL) is used between memory chip 111-114 and CODEC unit 140. In the approach of FIG. 3, the memory chip size remains practically the same, but in expense additional pins and circuitry are required for data links DL1-DLN. In both approaches of FIGS. 2 and 3, a dedicated CODEC unit 140 is used for each memory chip 111-114, which imposes certain restrictions on the data allocation management in memory controller 180. Such restrictions can result in reduced data rates and low utilization of CODEC units 140. Moreover, in the case of a memory chip failure, e.g., at the end of the memory lifetime, not only memory chip 111-114 but also the dedicated CODEC unit 140 are no longer operational from a system aspect.
U.S. Pat. No. 8,219,886 B1 describes a high density multi-level memory. The memory apparatus includes a memory block including a plurality of cells, each cell adapted to operate with multi-level signal. Such a memory apparatus also includes a channel block adapted to code data values in accordance with a coding scheme that favorably effects a distribution of the multi-levels of the multi-level signals, and to output the corresponding multi-level signals of the coded data values to the memory block.
US Patent Pub. No. 2008/0016269 A1 shows a flash/phase-change memory in multi-ring topology using serial-link packet interface. A multi-ring memory controller sends request packets to multiple rings of serial flash-memory chips. Each of the multiple rings has serial flash-memory chips with serial links in a uni-directional ring. Each serial flash-memory chip has a bypassing transceiver with a device ID checker that bypasses serial packets to a clock re-synchronizer and bypass logic for retransmission to the next device in the ring, or extracts the serial packet to the local device when an ID match occurs. Serial packets pass through all devices in the ring during one round-trip transaction from the controller. The average latency of one round is constant for all devices on the ring, reducing data-dependent performance, since the same packet latency occurs regardless of the data location on the ring. The serial links can be a Peripheral Component Interconnect (PCI) Express bus. Packets have modified-PCI-Express headers that define the packet type and data-payload length.
U.S. Pat. No. 8,244,961 B2 describes a SSD system with distributed processors. The system includes a serial data bus, a plurality of processors of a first type, and a processor of a second type. The serial data bus is configured to be coupled to a corresponding serial data bus of a host device. Each of the plurality of processors of the first type is coupled to a respective flash memory device. The processor of the second type is configured to manage the access that the plurality of the processors of the first type have to the serial data bus.
Accordingly, it is an aspect of the present invention to provide an improved memory system.